The MOS transistors configuring the semiconductor device are subject to variations during the manufacturing process. This leads to variations in leak currents and threshold voltages. Thus, there are variations in the operation speeds of the MOS transistors. For example, there may be large variations in operation speeds between a P-channel MOS transistor (PMOS transistor) and an N-channel MOS transistor (NMOS transistor) that configures an inverter circuit. As a result, a problem arises in that logical operations cannot be performed normally. That is, when, for example, the operation speed of the PMOS transistor is slow and the operation speed of the NMOS transistor is fast, the rising waveform of the output pulse from the inverter circuit becomes slack, and the falling waveform of the output pulse becomes acutely peaked. Thus, a problem arises in that the H level pulse width of the output pulse becomes narrower than the desired width.
Methods have been proposed for detecting variations in the operation speeds of MOS transistors by controlling the body bias (substrate voltage) of each MOS transistor based on the leak current in each MOS transistor, which correlates to the operation speed (refer, for example, to patent documents 1 and 2).
FIG. 8 is a block diagram showing the leak current detection circuit used in patent document 1. The leak current detection circuit for detecting the leak current in an NMOS transistor is described below. As shown in FIG. 8, a ring oscillator 70 includes a leak unit 71, a precharger 72, an amplification circuit 73, a delay circuit 74, and an even number of inverters 75. The leak unit 71 is configured by an NMOS transistor QN10. A low potential power VSS is normally applied to the gate of the transistor QN10 to inactivate the transistor QN10. A leak current flows between the source and drain of the transistor QN10 while the transistor QN10 is inactivated. The precharger 72 is configured by a PMOS transistor QP10 which is of a conduction type that differs from the NMOS transistor QN10. The amplification circuit 73 is coupled at a node X10 between the transistors QN10 and QP10, and a potential V10 at the node X10 is supplied to the amplification circuit 73. The amplification circuit 73 provides an output signal, which corresponds to the comparison result of a standard voltage VR and the potential V10 of the node X10, to the gate of the transistor QP10 through the delay circuit 74.
When a low potential power VSS level signal is provided to the gate of the transistor QP10, the transistor QP10 is activated and a load accumulates in a capacitor (line capacitor) at the node X10. Thus, the potential V10 of the node X10 supplied to the amplification circuit 73 gradually increases to a high potential power VDD (refer to charging time t1), as shown in FIG. 9. At this time, when the potential V10 becomes a high voltage exceeding the standard voltage VR, an H level output signal is output from the amplification circuit 73. The high potential power VDD level signal, which corresponds to this H level output signal, is supplied to the gate of the transistor QP10, thus inactivating the transistor QP10. Then, the load accumulated in the capacitor of the node X10 is discharged via the leak current flowing between the source and the drain of the transistor QP10. In this way, the potential V10 at the node X10 is gradually decreased (refer to discharge time t2), as shown in FIG. 9. When the potential V10 becomes less than the standard voltage VR, the output signal from the amplification circuit 73 shifts from an H level to an L level. Then, the low potential power VSS level signal corresponding to this L level output signal is provided to the gate of the transistor QP10, and the transistor QP10 is activated. Thus, a load again accumulates in the capacitor of the node X10. In this way, the charging time t1 and discharging time t2 are repeated, as shown in FIG. 9.
The output signal of the amplification circuit 73, which shifts so that the signal level alternates between an H level and an L level, is input to a leak current calculator 80. At this time, the H level output signal provided to the leak current calculator 80 is converted to a frequency which corresponds to the leak current. The leak current calculator 80 counts the input frequency via a counter circuit and calculates the leak current. Then, the body bias of the NMOS transistors of the semiconductor device are controlled based on the leak current calculated in the leak current calculator 80.
However, the H level output signal (frequency) includes not only a component of the leak current of the transistor QP10 (discharging time t2 component of FIG. 9) but also a component of the transistor QP10 relating to the charge of the node X10 (charging time t1 component in FIG. 9). When the leak current of the transistor QP10 is sufficiently less than the ON current of the transistor QP10, the discharging time t2 becomes sufficiently longer than the charging time t1, as shown in FIG. 9. The effect of the charging time t1 component is therefore small. However, when the leak current of the transistor QN10 increases, the leak current discharging time t2 decreases, as shown in FIG. 10. The effect of the charging time t1 component is therefore increased. In the leak current detection circuit of patent document 1, a problem therefore arises inasmuch as the leak current cannot be accurately measured through the influence of the transistor QP10, which is separate from the detection target NP10.
In order to solve the problem of abnormal operation of the inverter circuits resulting from variations in element characteristics described above, it is necessary to control the body bias of each MOS transistor by comparing the leak current of the NMOS transistor with the leak current of the PMOS transistor. Accordingly, in order to compare the leak current of each MOS transistor in the configuration described in patent document 1, a comparator circuit must be provided to compare the count value of the counter circuit of both leak current detection circuits and the leak current detection circuit of the PMOS transistor in addition to the leak current detection circuit of the NMOS transistor shown in FIG. 8. In patent document 1, therefore, problems arise in that increased circuit complexity and scale are unavoidable in order to compare the leak current of each MOS transistor.    Patent Document 1: U.S. Pat. No. 6,885,210    Patent Document 2: U.S. Pat. No. 6,882,172